A Reconfigurable Data Flow Architecture for Signal Processing Applications

Hans Hauer,
Fraunhofer Institut Integrierte Schaltungen, Am Wolfsmantel 33, 91058 Erlangen, Germany

DOI: 10.36724/2664-066X-2021-7-5-2-6

SYNCHROINFO JOURNAL. Volume 7, Number 5 (2021). P. 2-6.


This paper aims to devise a data flow model of computation for signal processing applications in which the operational nodes are signal/image processing functions such as Pixsum, Edge, Smooth [12]. These functions are configured during run time from a pool of reconfigurable FPGAS[4][5][6]. Thus because of the data flow model of computation, the signal processing functions execute concurrently. At the same time, these functions by exploiting their inherent spatial parallelism execute at high speed. There is a two fold speed up in the execution of image/signal processing applicationsone at the architecture level wherein a node of the dataflow model executes a digital signal processing (DSP) function rather than a low level machine operation. The second speed up is due to the fact that each DSP function is configured to execute in an FPGA by using maximally the concurrent operations that such a function permits. Another significant benefit that arises from our proposed architecture is that by reconfiguring an FPGA for a DSP function at run time, the reusability of the hardware elements results in reduced cost of operations. In this paper we provide an outline of the data flow architecture and its operational aspects.

KeywordsSemiconductor device modeling, RF IC Design, CMOS and BiCMOS circuit simulations, circuits for communications.


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