DESIGN AND OPTIMIZATION OF RADIX-4 BOOTH COMPLEX MULTIPLIERS USING CRA AND HAN-CARLSON ADDERS

S. Ram Babu,
Assistant Professor, Dept of ECE, Santhiram Engineering College, Nandyala, Andhra Pradesh, India;
Ramuluck@Gmail.com

Dr. Y. Mallikarjuna Rao,
Associate Professor, Dept of ECE, Santhiram Engineering College, Nandyala, Andhra Pradesh, India; arjunyamarthy@Gmail.com

K. Ruthvik,
Assistant Professor, Dept of ECE, Santhiram Engineering College, Nandyala, Andhra Pradesh, India;
Kummariruthvik@Gmail.com

S. Siddartha Reddy,
Assistant Professor, Dept of ECE, Santhiram Engineering College, Nandyala, Andhra Pradesh, India;
ssiddharthareddyreddy@Gmail.com

K. Durgesh,
Assistant Professor, Dept of ECE, Santhiram Engineering College, Nandyala, Andhra Pradesh, India;
Kurakudurgesh8@Gmail.com

K. Devendra Kumar,
Assistant Professor, Dept of ECE, Santhiram Engineering College, Nandyala, Andhra Pradesh, India;
Devendradeva9052@Gmail.com

DOI: 10.36724/2664-066X-2025-11-1-18-26

SYNCHROINFO JOURNAL. Volume 11, Number 1 (2025). P. 18-26.

Abstract

This research paper’s primary goal is to create an effective architecture for a radix-4 complex Vedic multiplier by utilizing the Han-Carlson adder to improve performance and overcome the shortcomings of the current designs. Conventional multipliers are better suited for lower-order bits, while the radix-4 Booth multiplication technique is usually employed for higher-bit-length applications because of its efficiency. In order to create a high-speed multiplier that can efficiently handle high-bit-length operations, this study integrates both strategies. By utilizing the Han-Carlson adder’s rapid carry generation capabilities and refining the handling of partial products, the drawbacks of current architectures — such as redundant calculations and additional time caused by intermediate remainders — are lessened. The Virtex-7 device family is the target of the Xilinx software used to implement the suggested design, which shows better speed and performance metrics than earlier approaches.

Keywords:  Xilinx software, Vedic multiplier, complex multiplier and cyclic redundant adder

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