A 36 mW, 13 b, 2.1 MS/s MULTI-BIT DS ADC IN 0.18 m DIGITAL CMOS PROCESS USING AN EFFICIENT TOP-DOWN DESIGN METHODOLOGY

Mona Safi-Harb,
Microelectronics & Computer Systems Laboratory, McGill University, Canada,
mona@macs.ece.mcgill.ca

Gordon W. Roberts,
Microelectronics & Computer Systems Laboratory, McGill University, Canada,
roberts@macs.ece.mcgill.ca

DOI: 10.36724/2664-066X-2021-7-4-7-11

SYNCHROINFO JOURNAL. Volume 7, Number 4 (2021). P. 7-11.

Abstract

A systematic method to design a switched-capacitor (SC) multi-bit DS ADC integrated circuit is presented. The modulator consists of a fourth-order, multi-stage (2-1-1) architecture, with a 3-bit fash ADC in the last stage only. The modulator building blocks specifcations were designed using a systematic top-down methodology. Trade-offs between circuit building block specifcations, optimization time and computing resources are derived. When sampled at 50 MHz, measured performance reveals an 81.3 dB dynamic range for an output Nyquist rate of 2.1 MS/s while using a single 1.8 V supply and dissipating 36 mW of power.

Keywords: switched-capacitor, multi-bit fash ADC, optimization time, computing resources, digital CMOS technology.

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