Design of a Low Latency Router for On-Chip Networks

Sumant Sathe, Daniel Wiklund, Dake Liu,
Dept. of Electrical Engineering, Linko..ping University, Sweden

DOI: 10.36724/2664-066X-2021-7-4-16-20

SYNCHROINFO JOURNAL. Volume 7, Number 4 (2021). P. 16-20.

Abstract

A problem with long on-chip wires is the resulting delays, and repeater insertion becomes essential to mitigate this problem. Point-to-point wiring leads to an increase in the area and repeater insertion leads to an increase in power consumption. The complexity of System-on-Chip (SoC) designs con- tinues to increase, and traditional bus-based intercon- nects will not be sufficient to manage the communication requirements of future billion transistor chips. The properties of our OCN are now reviewed. The OCN provides reliable communication. This is achieved by ensuring that data dropping is not allowed. On-Chip Network’s (OCN’s) provide a scalable alternative to existing on-chip interconnects. The key element of the OCN is the router. We present a prototype design of a 5-input, 5-output, scalable router. The router is constructed from a collection of parameterizable and reusable hardware blocks and is a basic building block of the OCN. The router supports wormhole routing, and is characterized by an area of 0.3 mm2 in 0.18 micron CMOS technology.

Keywords: System-on-Chip, On-Chip Network’s, On-Chip Network’s.

References

[1] P. Guerrier, A. Greiner. A generic architecture for on-chip packet interconnections, in DATE 2000.
[2] W. Dally, B. Towles. Route packets, not wires: On-chip interconnection networks, in DAC 2001.
[3] L. Benini, G. De Micheli. Networks on Chips: A New SoC Paradigm, IEEE Computer, 35(1):70-78, 2002.
[4] K. Goossens, et. al. Networks on silicon: Combining best-effort and guaranteed services, in DATE 2002.
[5] D. Wiklund, D. Liu. SoCBUS: Switched Network on Chip for Hard Real-Time Embedded Systems, in IPDPS 2003.
[6] E. Rijpkema, et. al. Trade Offs in the Design of a Router with both Guaranteed and Best-Effort Services for Networks on Chips, in DATE 2003.
[7] I. Saastamoinen, et. al. Interconnect IP Node for Future System-on-Chip Designs, IEEE Internal Workshop on Electronic Design, Test and Applications, 2002.
[8] P. Pande, et. al. Design of a Switch for Networks on Chip Applications, in ISCAS 2003.
[9] F. Mu, C. Svensson. Self-Tested Self-Synchronization