LOW COST IC TESTER USING PSEUDO-RANDOM APPROACH

Liakot Ali,
Dept. of Electrical and Electronic Engineering, Universiti Putra Malaysia (UPM), Serdang, Selangor, Malaysia,
liakot@eng.upm.edu.my

Roslina Sidek,
Dept. of Electrical and Electronic Engineering, Universiti Putra Malaysia (UPM), Serdang, Selangor, Malaysia, roslina@eng.upm.edu.my

Ishak Aris,
Dept. of Electrical and Electronic Engineering, Universiti Putra Malaysia (UPM), Serdang, Selangor, Malaysia,
ishak@eng.upm.edu.my

Mohd. Alauddin Mohd. Ali,
Dept. of Electrical, Electronic and Systems Engineering, Universiti Kebangsaan Malaysia (UKM), Bangi, Selangor, Malaysia, mama@eng.ukm.my

Bambang Sunaryo Suparjo,
Dept. of Electrical and Electronic Engineering, Universiti Putra Malaysia (UPM), Serdang, Selangor, Malaysia

DOI: 10.36724/2664-066X-2021-7-5-17-20

SYNCHROINFO JOURNAL. Volume 7, Number 5 (2021). P. 17-20.

Abstract

Low cost IC testing is now a burning issue in semiconductor technology. Conventional IC tester, ATE (automatic test equipment), cannot cope with the today’s continuously increasing complexities in IC technology. Deterministic algorithm, which is an idea of 1960’s, is adopted in the ATE. Recently pseudo-random testing approach has been emerged as an economically viable alternative to the expensive deterministic testing. This paper introduces a SOC implementing pseudo-random test technique for low cost IC testing with reliable performance. It is capable of testing combinational circuits as well as sequential circuits with scan-path facilities efficiently. It can also be used for testing PCB interconnection faults.

Keywords: ATE, Seed, LFSR, SOC.

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