Mona Safi-Harb, Gordon W. Roberts,
Microelectronics & Computer Systems Laboratory, McGill University, Canada
SYNCHROINFO JOURNAL. Volume 7, Number 3 (2021). P. 31-35.
The increasingly stringent requirements of today’s communication systems and portable devices are imposing two challenges on the design of high-resolution, high-speed ADCs and delta-sigma modulators (DSMs) in particular. The first is the extension of the input frequency range to include applications where the input bandwidth exceeds the 1 MHz range, while maintaining a feasible sampling frequency. The challenge in extending the operational speed of DSMs is further rendered more complicated by the ever shrinking transistor dimension, and in turn, the supply voltage, hence the second challenge. To address those two challenges, the DSMs presented in this paper targets a minimum of 12 bits in resolution at 2 MS/s Nyquist conversion rate, while using a single 1.8 V supply and minimum power dissipation.A switched-capacitor (SC) DS ADC integrated circuit (IC) with output rate slightly exceeding 2 MS/s was successfully implemented in a 1.8 V, 0.18 mm standard CMOS process. The IC consists of a fourth-order, multi-stage (2-1-1), single-bit modulator sampled at an oversampling rate of 50 MHz. Special effort has been made to reduce the power consumption of the modulator through careful system-level modeling and synthesis of circuit specifcations. Experimental results reveal a 77.6 dB dynamic range while consuming 18.8 mW of power, making it the lowest power dissipation for output rates in excess of 2 MS/s.
Keywords: digital cmos process, portable devices, feasible sampling frequency.
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