LOW POWER DIGITAL CMOS VLSI CIRCUITS DESIGN WITH DIFFERENT HEURISTIC ALGORITHMS

Wladyslaw Szczesniak,
Faculty of Electronics, Telecommunications, and Informatics, Gdansk University of Technology, Gdansk, Poland, wlad@ue.eti.pg.gda.pl

Piotr Szczesniak,
Faculty of Electronics, Telecommunications, and Informatics, Gdansk University of Technology, Gdansk, Poland; R&D Marine Technology Centre, Gdynia, Poland
piotr@ue.eti.pg.gda.pl

DOI: 10.36724/2664-066X-2021-7-4-30-34

SYNCHROINFO JOURNAL. Volume 7, Number 4 (2021). P. 30-34.

Abstract

The growing demand for portable computing devices leads to new electronic systems fulfilling the requirements for the low power dissipation in the chip. Although, reduction of supply voltage is one of the most effective techniques of decreasing the power consumption in digital CMOS VLSI circuits it results in chip throughput degradation. This paper presents three versions of the Inserting Idle Operation with Interchanging heuristic algorithm, namely simple IIOI, MAximal RELativity (MAREL) and UNIform LOad (UNILO). They are applied to the high-level synthesis of CMOS VLSI circuits with power reduction. Comparison of the obtained results for the chosen set of benchmarks show the different levels of power reduction obtained by different algorithms applied. For different benchmarks the power reduction reaches up to 15%, and up to 68% with extending latency by 50%.

Keywords: Low power design, VLSI digital circuits, high level synthesis and low power design, heuristic algorithms.

References

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