High Power Amplifier Predistorter ASIC in Standard Digital CMOS Technology

H. Tap-Beteille,
LEN7/ENSEEIHT, Toulouse, France

D. Roviras,
TeSA/IRIT/ENSEEIHT, Toulouse, France

M. Lescure,
LEN7/ENSEEIHT, Toulouse, France

A. Mallet,
CNES, Toulouse, France

DOI: 10.36724/2664-066X-2021-7-4-35-39

SYNCHROINFO JOURNAL. Volume 7, Number 4 (2021). P. 35-39.


Satellite communications offer a wide coverage for global communication systems. In order to increase spectral efficiency, non constant modulus constellations are very attractive compared to the classical BPSK and QPSK schemes. A 16-QAM modulation could offer a significant increase in spectral efficiency for satellite communications. Because the available power on board the satellite is strongly limited, High Power Amplifiers (HPA) like Travelling Wave Tubes (TWT) or Solid State Power Amplifiers (SSPA) are generally operated near the saturation point with a low back off. When operated with such low back off, HPA are highly non linear amplifiers. So, the signal to amplify being strongly distorted, a predistorter has been developed. A high power amplifier predistorter has been implemented in 0.6 m CMOS technology. First, the predistorter is briefly described. Then, the implementation of the predistorter is shown. The circuits designed for the neuron first layer are described, as well as the simulation results obtained.

KeywordsHigh power amplifier, MLP neural network predistorter, Gilbert cell, Kirshoff adder, analog circuits, 0.6 m CMOS technology.


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